[scilab-Users] Scicos Block with Different Output Port Types?

[Simone Mannori]

Hello,

please try to use this "define" section in the interfacing function
TEST.sce

  case 'define' then
    // computational function
    model=scicos_model()
    model.sim=list('test',4)
  
    // inputs
    model.in = -1 ; 
    model.in2= -2 ;

    // outputs
    model.out  = [-1;-1]
    model.out2 = [-2;-2]
  
    model.blocktype='c'
    model.firing=[]
    model.dep_ut=[%t,%f]
    model.label=''
    model.nzcross=0
    model.nmode=0
    model.equations=list()

    exprs=[]
    
    // icon
    gr_i = list(["x=orig(1)+sz(1)*0.1;y=orig(2)+sz(2)*0.3;";
                 "w=sz(1)*0.8;h=sz(2)*0.4;";
                 "xstringb(x,y,""TEST"",w,h,''fill'');"],..
                 8 )
    x=standard_define([2,2],model,exprs,gr_i)

Also the section "set" needs some attention.

Can you be so kind to send me "test.c" ?

I will be happy to debug fully your Scicos block, create a "reference"
template and put it on line.

Thanks in advance for your help.

Simone Mannori

 



 


On Mon, 2008-03-10 at 10:22 +0100, Dirk Reusch wrote:
> Hello everybody,
> 
> I am using Scilab 4.1.2/Scicos 4.2 under Linux.
> 
> I've tried to build a scicos block with two outputs ports.
> The first is of type 1 (double) and the second is of type 3
> (int32).
> 
> Editing a diagram, i.e. connecting these ports with ports of
> other blocks of corresponding types works just fine.
> 
> But, scicos compilation/simulation does not work! The compiler
> "thinks" that the second output port has type 1 and _not_ 3.
> 
> Is that a bug, a limitation, or have I done something wrong?
> 
> I've attached a small example, which should reproduce the
> described behaviour.
> 
> Best Regards,
> 
> Dirk Reusch